The typical technique to manufacture semiconductor chips involves layering a first layer metallic pattern on top of a first layer dielectric base. As soon as the first layer metallic pattern is tested for proper electrical conductivity characteristics, a second layer dielectric base is formed on top of the first layer dielectric base and metallic pattern. A second layer metallic pattern is thereupon layered on top of the second layer dielectric base, and the electrical characteristics of the second layer metallic pattern is then tested. This process is continued for each of the subsequent layers of dielectric base and metallic pattern. At different stages during the semiconductor chip manufacturing process, a connecting stud (also known as an electric via) extends through one or more layers in such a manner that an electrically conductive connection is formed between the metallic patterns of different layers of the semiconductor chip.
Electronic testing of each layer of the metallic pattern (which forms the electrically conductive pathways) becomes more involved as the electronic chips become more sophisticated. Once a subsequent layer of dielectric base is layered on top of a specific layer of metallic pattern, the only technique by which the metallic pattern can be modified is to remove each subsequent layer(s) of metallic patterns and dielectric base (all the work associated with the subsequent layers is wasted.) For this reason, it is important to be certain that each layer of metallic pattern is functioning properly before the next layer of dielectric base is laid down.
If the electrical and/or optical characteristics of the metallic layer which is being tested are faulty or questionable, it may be desired to remove all or part of the metallic pattern in the metallic layer being tested, and to replace the removed metallic layer with another metallic layer which is functioning properly. The process of removing the faulty metallic pattern and replacing it with a new layer of metallic pattern is known in the art as "re-working" the metallic layer. The process of removing an entire metal layer, or a portion of a metal layer is known as "reclamation". These terms are used throughout this disclosure.
During re-working or reclamation of the metallic layer, it is desirable to completely remove the metallic layer while removing or distorting very little of the original dielectric base and any connecting studs which are presently in place. Distorted dielectric bases can result in a difficulty in forming the next metallic layer. Additionally, electronic requirements specify the proper dimensioning of each layer of dielectric base, metallic layer, and the proper size and shapes of the connecting studs. Therefore, if the reworking or the reclamation process removes too much of the dielectric base or the connecting stud, then the defective portion will have to be replaced, (and perhaps the entire electronic chip will have to be scrapped).
Present techniques to reclaim or rework metallic layers include utilizing an acid planarization process to remove the metallic layers. These techniques typically work adequately if there is only a single re-work process or reclaiming being performed on top of each dielectric base layer, since an allowable amount of dielectric will be removed in a single process. However, as the electronic circuitry becomes more complex; the dimensions of the metallic conductor lines become smaller; the overall dimensions of the circuitry associated with each metallic layer increases; and/or the possibility for mistakes for each layer of electronic layer increases. Thus, the probability for multiple re-works also increases. It therefore becomes desirable to provide some technique which would permit more than a single rework to any metallic layer.
From the above, it can be envisioned that providing some reclamation or re-work technique which does not remove or distort excessive amounts of dielectric layer material, or connecting stud material, would be highly desirable. This technique becomes more significant, in general, as the semi-conductor chips become more complex, and the necessity for multiple re-working or reclamation processes increases on top of a single dielectric layer.